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integrated circuit systems, inc. general description features ics9148-11 block diagram pentium is a trademark of intel corporation i 2 c is a trademark of philips corporation frequency generator & integrated buffers for pentium tm 9148-11 revb 12/09/97p pin configuration the ics9148-11 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro. an output enable pin is provided for testability. mode allows power management functions: cpu_stop#, pci_stop# & pwr_dwn#. high drive bclk outputs typically provide greater than 1 v/ns slew rate into 30 pf loads. pclk outputs typically provide better than 1v/ ns slew rate into 20 pf loads while maintaining 50 5% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. ? generates four processor, six bus, one 14.31818mhz and 12 sdram clocks. ? synchronous clocks skew matched to 250ps window on cpu, sdram and 500ps window on bus clocks. ? cpuclks to bus clocks skew 1-4 ns (cpu early) ? test clock mode eases system design ? custom configurations available ? vdd(1:3) - 3.3v 10% (inputs 5v tolerant w/series r ) ? vddl(1:2) - 2.5v or 3.3v 5% ? pc serial configuration interface ? power management control input pins ? 48-pin ssop package 48-pin ssop functionality oe cpuclk, sdram (mhz) x1, ref (mhz) pciclk (mhz) 0 high-z high-z high-z 1 66.6 14.318 33.3 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9148-11 pin descriptions power groups vdd1 = ref0, x1, x2 vdd2 = pciclk_f, pciclk (0:5) vdd3 = sdram (0:4) (8:11) sdram5/pwr_dwn#, sdram6/cpu_stop#, sdram7/pci_stop#, supply for pll core. vddl1 = ioapic (0:1) vddl2 = cpuclk (0:3) pin number pin name type description 2 ref0 out 14.318 mhz reference clock outputs. 3, 9, 16, 22, 27, 33, 39, 45 gnd pwr ground. 4x1 in xtal_in 14.318mhz crystal input, has internal 33pf load cap and feed back resistor from x2 5 x2 out xtal_out crystal output, has internal load cap 33pf 25 mode in mode select pin for enabling power management features. 7 pclk_f out free running bus clock during pci_stop# = 0. 8, 10, 11, 12 13, 15 pciclk (0:5) out bus clock outputs. 26 oe in logic input for output enable, tristates all outputs when low. 23 sdata in serial data in for serial config port. 24 sclk in clock input for serial config port. 1, 6, 14, 19, 30, 36, vdd1, vdd2, vdd3 pwr nominal 3.3v power supply, see power groups for function. 17, 18, 20, 21, 32, 34, 35, 37, 38 sdram (0:4) (8:11) out sdram clocks 66.6mhz. 42, 48 vddl2, vddl1 pwr cpu and ioapic clock power supply, either 2.5 or 3.3v nominal 40, 41, 43, 44 cpuclk (0:3) out cpu output clocks, powered by vddl2 (66.6 mhz) 46, 47 ioapic (0:1) out ioapic clock output, (14.318 mhz) powered by vddl1 28 sdram7 out sdram clock 66.6 mhz selected pci_stop# in halts pciclk (0:5) at logic "0" level when low 29 sdram6 out sdram clock 66.6 mhz selected cpu_stop# in halts cpuclk clocks at logic "0" level when low 31 sdram5 out sdram clock 66.6 mhz selected pwr_dwn# in powers down chip, active low
3 ics9148-11 power-on conditions example: a) if mode = 1, pins 28, 29 and 31 are configured as sdram7, sdram6 and sdram5 respectively. b) if mode = 0, pins 28, 29 and 31 are configured as pci_stop#, cpu_stop# and pwr_dwn# respectively. power-on default conditions at power-up and before device programming, all clocks will default to an enabled and ?on? condition. the frequencies that are t hen produced are on the fs and mode pin as shown in the table below. clock default condition at power-up ref 0 14.31818 mhz ioapic (0:1) 14.31818 mhz mode pin # description function 1 44, 43, 41, 40 cpuclks 66.6 mhz - w/serial config enable/disable 38, 37, 35, 34, 32, 31, 21, 20, 18, 17, 29, 28 sdram 66.6 mhz - all sdram outputs 8, 10, 11, 12, 14, 15, 7 pciclks 33.3 mhz - w/serial config enable/disable 0 28 pci_stop# power management, pci (0:5) clocks stopped when low 29 cpu_stop# power management, cpu (0:3) clocks stopped when low 31 sdram/pwr _dwn# used as pwr_dwn# when low 7 pciclk_f 33.3 mhz - 33.3 mhz - pci clock free running for power management 44, 43, 41, 40 cpuclks 66.6 mhz - cpu clocks w/external stop control and serial config individual enable/disable. 38, 37, 35, 34, 32, 21, 20, 18, 17 sdram 66.6 mhz - sdram clocks w/serial config individual enable/disable. 8, 10, 11, 12, 14, 15 pciclks 33.3 mhz - pci clocks w/external stop control and serial config individual enable/disable.
4 ics9148-11 vdd(1,2,3) this is the power supply to the internal core logic of the device as well as the clock output buffers for ref(0:1), pciclk, 48/24mhza/b and sdram(0:7). this pin operates at 3.3v volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. vddl1,2 this is the power supplies for the cpuclk and ioapci output buffers. the voltage level for these outputs may be 2.5 or 3.3volts. clocks from the buffers that each supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the dc parameter table in this data sheet. gnd this is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. x1 this input pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. with a nominal value fo 33pf no external load cap is needed for a c l =17 to 18pf crystal. x2 this output pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. the x2 pin will also implement an internal crystal loading capacitor nominally 33pf. cpuclk (0:3) these output pins are the clock outputs that drive processor and other cpu related circuitry that requires clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks are controlled by the voltage level applied to the vddl2 pin of the device. see the functionality table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. sdram(0:11) these output clocks are use to drive dynamic ram?s and are low skew copies of the cpu clocks. the voltage swing of the sdram?s output is controlled by the supply voltage that is applied to vdd3 of the device, operates at 3.3 volts. ioapic (0:1) this output is a fixed frequency output clock that runs at the reference input (typically 14.31818mhz) . its voltage level swing is controlled by vddl1 and may operate at 2.5 or 3.3volts. technical pin function descriptions ref0 the ref output is a fixed frequency clock that runs at the same frequency as the input reference clock x1 or the crystal (typically 14.31818mhz) attached across x1 and x2. pciclk_f this output is equal to pciclk(0:5) and is free running, and will not be stopped by pci_stp#. pciclk (0:5) these output clocks generate all the pci timing requirements for a pentium/pro based system. they conform to the current pci specification. they run at 1/2 cpu frequency. mode this input pin is used to select the input function of the i/o pins. an active low will place the i/o pins in the input mode and enable those stop clock functions. pwr_dwn# this is an asynchronous active low input pin used to power down the device into a low power state by not removing the power supply. the internal clocks are disabled and the vco and crystal are stopped. powered down will also place all the outputs in a low state at the end of their current cycle. the latency of power down will not be greater than 3ms. the i 2 c inputs will be tri-stated and the device will retain all programming information. this input pin only valid when mode=0 (power management mode) cpu_stop# this is a synchronous active low input pin used to stop the cpuclk clocks in an active low state. all other clocks including sdram clocks will continue to run while this function is enabled. the cpuclk?s will have a turn on latency of at least 3 cpu clocks. this input pin only valid when mode=0 (power management mode) pci_stop# this is a synchronous active low input pin used to stop the pciclk clocks in an active low state. it will not effect pciclk_f nor any other outputs. this input pin only valid when mode=0 (power management mode) i 2 c the sdata and sclock inputs are use to program the device. the clock generator is a slave-receiver device in the i 2 c protocol. it will allow read-back of the registers. see configuration map for register functions. the i 2 c specification in philips i 2 c peripherals data handbook (1996) should be followed. oe output enable tristates the outputs when held low. this pin will override the i 2 c byte 0 function, so that the outputs will be tristated when the oe is low regardless of the i 2 c defined function. when oe is high, the i 2 c function is in active control.
5 ics9148-11 serial configuration command bitmaps byte 0: functional and frequency select clock register (default=0) general i 2 c serial interface information bit pin# description pwd bit 7 - reserved 0 bit 6 - must be 0 for normal operation 0 bit 5 - must be 0 for normal operation 0 in spread spectrum, controls type (0=centered, 1=down spread) 0 bit 4 - must be 0 for normal operation 0 in spread spectrum, controls spreading (0=1.8%, 1=0.6%) 0 bit 3 - reserved 0 bit 2 - reserved 0 bit 1 bit 0 - bit1 1 1 0 0 bit0 1 - tri-state 0 - spread spectrum enable 1 - testmode 0 - normal operation 0 0 note: pwd = power-up default a. for the clock generator to be addressed by an i 2 c controller, the following address must be sent as a start sequence, with an acknowledge bit between each byte. b. the clock generator is a slave/receiver i 2 c component. it can "read back "(in philips i 2 c protocol) the data stored in the latches for verification. (set r/w# to 1 above). there is no byte count supported, so it does not meet the intel smb piix4 protocol. c. the data transfer rate supported by this clock generator is 100k bits/sec (standard mode) d. the input is operating at 3.3v logic levels. e. the data byte format is 8 bit bytes. f. to simplify the clock generator i 2 c interface, the protocol is set to use only block writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. g . in the power down mode (pwr_dwn# low), the sdata and sclk pins are tristated and the internal data latches maintain all prior programming information. h. at power-on, all registers are set to a default condition. see byte 0 detail for default condition, bytes 1 through 5 default to a 1 (enabled output state) then byte 0, 1, 2, etc in sequence until stop. byte 0, 1, 2, etc in sequence until stop. clock generator address (7 bits) ack + 8 bits dummy command code ack + 8 bits dummy byte count ack a(6:0) & r/w# d2 (h) clock generator address (7 bits) ack byte 0 ack byte 1 ack a(6:0) & r/w# d3 (h)
6 ics9148-11 byte 1: cpu clock register select functions notes: 1. ref is a test clock on the x1 inputs during test mode. notes: 1 = enabled; 0 = disabled, outputs held low byte 2: pciclk clock register byte 4: sdram clock register notes: 1 = enabled; 0 = disabled, outputs held low notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pwd description bit 7 - 1 reserved bit 6 7 1 pciclk_f (act/inact) bit 5 15 1 pciclk5 (act/inact) bit 4 13 1 pciclk4 (act/inact) bit 3 12 1 pciclk3 (act/inact) bit 2 11 1 pciclk2 (act/inact) bit 1 10 1 pciclk1 (act/inact) bit 0 8 1 pciclk0 (act/inact) bit pin# pwd description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 - 1 reserved bit 3 17 1 sdram11 (act/inact) bit 2 18 1 sdram10 (act/inact) bit 1 20 1 sdram9 (act/inact) bit 0 21 1 sdram8 (act/inact) bit pin# pwd description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 - 1 reserved bit 3 40 1 cpuclk3 (act/inact) bit 2 41 1 cpuclk2 (act/inact) bit 1 43 1 cpuclk1 (act/inact) bit 0 44 1 cpuclk0 (act/inact) byte 3: sdram clock register notes: 1 = enabled; 0 = disabled, outputs held low function description outputs cpu pci, pci_f sdram ref ioapic tri - state hi-zhi-zhi-zhi-zhi-z test mode tclk/2 1 tclk/4 1 tclk/2 1 tclk 1 tclk 1 bit pin# pwd description bit 7 28 1 sdram7 (act/inact) desktop only bit 6 29 1 sdram6 (act/inact) desktop only bit 5 31 1 sdram5 (act/inact) desktop only bit 4 32 1 sdram4 (act/inact) bit 3 34 1 sdram3 (act/inact) bit 2 35 1 sdram2 (act/inact) bit 1 37 1 sdram1 (act/inact) bit 0 38 1 sdram0 (act/inact) note: pwd = power-up default
7 ics9148-11 power management ics9148-11 power management requirements clock enable configuration full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. the first cloc k pulse coming out of a stopped clock condition may be slightly distorted due to clock network char ging circuitry. board routing and signal loading may have a large impact on the initial clock distortion also. notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . 3. power up latency is when pd# goes inactive (high) to when the first valid clocks are output by the device. 4. power down has controlled clock counts applicable to cpuclk, sdram, pciclk only. the ref and ioapic will be stopped independant of these. signal signal state latency no. of rising edges of free running pciclk cpu_ stop# 0 (disabled) 2 1 1 (enabled) 1 1 pci_stop# 0 (disabled) 2 1 1 (enabled) 1 1 pwr_dwn# 1 (normal operation) 3 3ms 0 (power down) 4 2max byte 5: peripheral clock register notes: 1 = enabled; 0 = disabled, outputs held low bit pin# pwd description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 46 1 ioapic1 (act/inact) bit 4 47 1 ioapic0 (act/inact) bit 3 - 1 reserved bit 2 - 1 reserved bit 1 - 1 reserved bit 0 2 1 ref0(act/inact) cpu_stop# pci_stop# pwr_dwn# cpuclk pciclk other clocks, sdram, ref, ioapics crystal vcos x x 0 low low stopped off off 0 0 1 low low running running running 0 1 1 low 33.3 mhz running running running 1 0 1 66.6 mhz low running running running 1 1 1 66.6 mhz 33.3 mhz running running running byte 6: optional register for future notes: 1. byte 6 is reserved by integrated circuit systems for future applications. bit pin# pwd description bit 7 - 1 reserved bit 6 - 1 reserved bit 5 - 1 reserved bit 4 - 1 reserved bit 3 - 1 reserved bit 2 -1 reserved bit 1 - 1 reserved bit 0 - 1 reserved note: pwd = power-up default
8 ics9148-11 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9148-11 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ics9148-11 internally. the minimum that the pciclk (0:5) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:5) clocks. pciclk (0:5) clocks are stopped in a low state and started with a full high pulse width gua ranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock. cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop # is synchronized by the ics9148-11 . the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a mann er that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. (drawing shown on next page.) notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9148-11. 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state.
9 ics9148-11 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internal by the ics9148-11 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the power on latency is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals during the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the ics9148. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9148. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state.
10 ics9148-11 absolute maximum ratings supply v oltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . . . 0c to +70c storage t emperature . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliabili ty. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unles s otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a operating i dd3.3op c l = 0 pf; select @ 66m 75 95 ma supply current outputs disabled i dd3.3oe c l = 0 pf; with input address to vdd or gnd 18 25 ma supply current input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 5 3 ms t cpu-sdram2 v t = 1.5 v 200 500 ps skew 1 t cp u-p ci2 v t = 1.5 v 1 2 4 ns t ref-ioapic v t = 1.5 v 900 ps
11 ics9148-11 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwis e s tated) parameter symbol conditions min typ max units operating i dd2.5op c l = 0 pf; select @ 66m 6 8 9.5 ma supply current t cp u-sdram2 v t = 1.5 v; v tl = 1.25 v; sdram leads 250 500 ps skew 1 t cp u-p ci2 v t = 1.5 v; v tl = 1.25 v; cpu leads 1 2 4 ns t ref-ioapic v t = 1.5 v; v tl = 1.25 v; cpu leads 860 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 15 45 w output impedance r dsn2b 1 v o = v dd *(0.5) 15 45 w output high voltage v oh2b i oh = -12.0 ma 2 2.6 v output low voltage v ol2b i ol = 12 ma 0.3 0.4 v output high current i oh2b v oh = 1.7 v -25 -16 ma output low current i ol2b v ol = 0.7 v 19 26 ma ris e time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.7 2 ns fall time t f2 b 1 v oh = 2.0 v, v ol = 0.4 v 1.5 2 ns duty cycle d t2b 1 v t = 1.25 v 45 50 55 % skew t sk2b 1 v t = 1.25 v 60 250 ps t jcyc-cyc2b 1 v t = 1.25 v 150 250 ps jitter t j1s2b 1 v t = 1.25 v 30 150 ps t jabs2b 1 v t = 1.25 v -250 80 +250 ps 1 guarenteed by design, not 100% tested in production.
12 ics9148-11 electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 10 30 w output impedance r dsn4b 1 v o = v dd *(0.5) 10 30 w output high voltage v oh4\b i oh = -18 ma 2 2.4 v output low voltage v ol4b i ol = 18 ma 0.45 0.5 v output high current i oh4b v oh = 1.7 v -25 -16 ma output low current i ol4b v ol = 0.7 v 19 26 ma ris e time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 1.4 1.6 ns fall time t f4 b 1 v oh = 2.0 v, v ol = 0.4 v 1.2 1.6 ns duty cycle d t4b 1 v t = 1.25 v 40 54 60 % t jcyc-cyc4b 1 v t = 1.25 v 1400 ps jitter t j1s4b 1 v t = 1.25 v 300 400 ps t jabs4b 1 v t = 1.25 v -1000 800 1000 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - ref0 t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 45 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output impedance r dsp7 v o = v dd *(0.5) 10 24 w output impedance r dsn7 v o = v dd *(0.5) 10 24 w output high voltage v oh7 i oh = -30 ma 2.6 2.75 v output low voltage v ol7 i ol = 23 ma 0.3 0.4 v output high current i oh7 v oh = 2.0 v -62 -54 ma output low current i ol7 v ol = 0.8 v 42 50 ma ris e time t r7 1 v ol = 0.4 v, v oh = 2.4 v 0.9 2 ns fall time t f7 1 v oh = 2.4 v, v ol = 0.4 v 0.9 2 ns duty cycle d t7 1 v t = 1.5 v 40 54 60 % t jcyc-cyc7b 1 v t = 1.25 v 1400 ps jitter t j1s7b 1 v t = 1.25 v 350 ps t jabs7b 1 v t = 1.25 v -1000 900 1000 ps 1 guarenteed by design, not 100% tested in production.
13 ics9148-11 electrical characteristics - pci t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -11 ma 2.6 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.15 0.4 v output high current i oh1 v oh = 2.0 v -65 -54 ma output low current i ol1 v ol = 0.8 v 40 54 ma ris e time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle d t1 1 v t = 1.5 v 45 50 55 % skew t sk1 1 v t = 1.5 v 200 500 ps jitter t j1s1 1 v t = 1.5 v 10 150 ps t jabs1 1 v t = 1.5 v -250 65 250 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwis e s tated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 w output impedance r dsn3 1 v o = v dd *(0.5) 10 24 w output high voltage v oh3 i oh = -30 ma 2.6 2.8 v output low voltage v ol3 i ol = 23 ma 0.3 0.4 v output high current i oh3 v oh = 2.0 v -67 -54 ma output low current i ol3 v ol = 0.8 v 40 55 ma ris e time t r3 1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 1.4 2 ns duty cycle d t3 1 v t = 1.5 v 45 50 55 % skew t sk3 1 v t = 1.5 v 200 500 ps jitter t j1s3 1 v t = 1.5 v 50 150 ps t jabs3 1 v t = 1.5 v -250 100 250 ps 1 guarenteed by design, not 100% tested in production.
14 ics9148-11 ssop package ordering information ICS9148F-11 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device t ype (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx f - ppp symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 a2 .088 .090 .092 b .008 .010 .0135 c.005- .010 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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